Level conversion circuit

ABSTRACT

A level conversion circuit for converting a signal of a polarity to a signal of the opposite polarity has differential pair transistors, push-pull type output transistors adapted to receive the differential outputs of opposite phases from the differential pair transistors, a plurality of protective transistors for protecting the output transistors and a capacitance separation element connected between the common collector outputs of the plurality of protective transistors and the output of one of the differential pair transistors. The protective transistor prevents both of the differential outputs from simultaneously taking high level due to various operating conditions of the conversion circuit. Therefore, the deterioration or breakdown of the output transistors caused by the through current is avoided. The capacitance separation element also contributes to prevent the reduction of operation speed of the differential transistors caused by the collector capacitances of the plurality of protective transistors.

LIST OF PRIOR ART

The following reference is cited to show the state of the art:

(1) Japanese Patent Laid-Open No. 98749/1975.

BACKGROUND OF THE INVENTION

The present invention relates to a level conversion circuit.

It is necessary to incorporate a level conversion circuit between theoutput of an emitter-coupled-logic circuit (referred to as ECL,hereinafter) and the input of a circuit, such as a transistor-transistorlogic circuit (referred to as TTL, hereinafter) or an N-channelinsulated gate field effect transistor (referred to as N-MOS).

Namely, an ECL circuit is operated typically by a negative sourcevoltage, and its signal level changes within a negative voltage regionwith respect to the grounding potential of the circuit. On the otherhand, a circuit such as a TTL circuit, a N-MOS circuit or the likeoperates with a positive power source voltage and the signal levelchanges within a positive voltage region with respect to the groundingpotential of the circuit. Therefore, an interface must be providedbetween the output of the first circuit operating with a negativevoltage and the input of the second circuit operating with positivesource voltage.

In order to achieve high-speed operation and to reduce the powerconsumption, the level conversion circuit may be constituted bydifferential transistors adapted to receive two input signals of ECLsignal level and transistors of single end push-pull constructionadapted to receive differential output signals of reverse phaseslevel-shifted by these differential transistors.

The differential outputs take a high level when both of theabove-mentioned two inputs signal are open, so that the transistors ofthe single end push-pull arrangement are turned on. In order to avoidthis, it is necessary to incorporate an input protecting transistor inthe circuit.

In addition, since the level conversion circuit operates with twovoltages of positive and negative levels, it is possible that bothlevel-shift outputs may take a high level at the time of turning on ofthe power supply or due to a fluctuation of the applied voltage,resulting in a breakdown or deterioration of the push-pull outputtransistors due to an overcurrent in the latter. It is, therefore,necessary to employ another protective transistor for forciblymaintaining one level shift output substantially at the groundingpotential.

The present inventors have found that, since these protectivetransistors are connected at their collectors to the differential outputnode, the parasitic capacitance of the differential output node isincreased to lower the operation speed.

SUMMARY OF THE INVENTION

It is, therefore, an object of the invention to provide a levelconversion circuit which operates stably and at a high speed.

According to a basic feature of the invention, the collectorcapacitances of a plurality of protective transistors are separated fromthe differential output capacitance by means of capacitance separatingelements which comprise either a transistor or a Schottky diode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an embodiment of the invention;

FIG. 2 is an illustration explanatory of the operation of the circuitshown in FIG. 1;

FIG. 3 is a circuit diagram of another embodiment of the invention;

FIG. 4 is an equivalent circuit diagram explanatory of the circuit shownin FIG. 3;

FIG. 5 shows wave forms of signals in the circuit shown in FIG. 4; and

FIG. 6 is an equivalent circuit diagram explanatory of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the invention will be fully described through preferredembodiments.

Referring first to FIG. 1, a level conversion circuit in accordance withan embodiment of the invention is, but not exclusively, formed as amonolithic semiconductor integrated circuit (IC) having externalterminals P₁ to P₇.

The terminal P₁ is supplied with a positive source voltage V_(cc) of,for example +5 V, while the terminal P₇ receives a negative sourcevoltage -V_(EE) of, for example, -5.2 V. The terminal P₃ is maintainedat the grounding potential GND of the circuit.

In FIG. 1, the portion 1 enclosed by two-dot-and-dash line constitutes alevel conversion section, while portions 2,3 enclosed also bytwo-dot-and-dash lines constitute biasing sections. Portions 4-1, 4-2and 5 constitute a source voltage detecting section.

The biasing section 2 includes resistors R₇ to R₁₀, transistor Q₄ anddiodes D₁₁ to D₁₃, and is connected between the terminal P₁ and P₇.

This biasing section 2 generates bias voltages at the nodes N₃ to N₅,respectively, upon receipt of the positive and negative source voltagesV_(cc) and -V_(EE).

The bias voltage of the node N₃ is used as the bias voltage for a sourcevoltage detecting section 5, and is selected to be smaller than the sum2 V_(BE) of the base-emitter forward voltages V_(BE) of the transistorsQ₆ and Q₈ of the source voltage detecting section 5 when the sourcevoltage V_(cc) and -V_(EE) are within correct ranges, and is made higherthan 2 V_(BE) when the positive source voltage V_(cc) has been increasedbeyond the correct level and when the absolute value of the negativesource voltage -V_(EE) has come down below the correct level. Thebiasing voltage of the node N₄ is used as the biasing voltage for thebase of the transistor Q₁₂ in the level conversion section 1. This basebiasing voltage is selected to be lower than the level of the ECL signalapplied to the external terminal P₄ or P₅ of the IC.

The bias voltage of the node N₅ is used as the biasing voltage for thetransistor Q₁₀ of the biasing section 3.

The biasing section 3 is constituted by resistors R₁₅ to R₁₇, diodesD₁₄, D₁₅ and transistors Q₉, Q₁₀, and is connected between the groundingpoint GND of the circuit and the negative source terminal P₇. Thisbiasing section 5 generates bias voltages at the nodes N₆ and N₇,respectively. The biasing voltage V_(B) at the node N₆ is set to amedium level of the ECL signal level. For instance, if the high and lowlevels of the ECL signal are determined to be -0.89 V and -1.69 V,respectively, the reference bias voltage V_(B) at the node N₆ isselected to be -1.29 V by a suitable setting of the resistors R₁₅ andR₁₆.

The bias voltage at the node N₇ is used as the base bias voltage for thecurrent source transistor Q₁₅ of the level conversion section 1.

The level conversion section 1 is constituted mainly by a current sourcetransistor Q₁₅ having an emitter resistance R₂₄, differential pairtransistors Q₁₃, Q₁₄, collector load resistors R₁₉, R₂₀ for respectivedifferential pair transistors, single end push-pull transistors Q₁₆ toQ₁₉ in the form of darlington connection, and resistors R₂₁ to R₂₃, andis connected between the power supply terminals P₁ and P₇.

The level conversion section 1 further has a transistor Q₂₀ andresistors R₂₅, R₂₆ which are specifically provided for enhancing theoperation speed in accordance with the technical idea of the presentinvention.

Although not exclusive, the terminal P₄ is adapted to be supplied withan output signal A coming from an ECL circuit which is not shown, whilethe terminal P₅ receives the reference biasing voltage V_(B) which issupplied by the biasing section 3 via the terminal P₆, by means ofillustrated connection between the terminals outside the IC.

As a result, the differential pair transistors Q₁₃ and Q₁₄ make adifferential operation in accordance with the ECL signal A supplied tothe terminal P₄.

Namely, the transistors Q₁₃ and Q₁₄ are conductive and non-conductive,respectively, when the ECL signal A takes the low level. In this state,an electric current is supplied to the constant-current transistor Q₁₅from the resistor R₁₉, through the transistor Q₁₃. The resistance valueof the resistor R₁₉ and the constant current of the current sourcetransistor Q₁₅ are beforehand selected suitably, such that the node N₁takes substantially grounding potential GND, e.g. a low level of +0.3 V.

In contrast to the above, the node N₂ is made to take the high levelsubstantially equal to the positive source voltage V_(cc), by thenon-conductive state of the differential transistor Q₁₄. Due to the lowlevel of the node N₁, the transistors Q₁₈ and Q₁₉ of darlingtonconnection are turned off, while the transistors Q₁₆, Q₁₇ are turned onas the node N₂ take the high level. In consequence, a high level signalof substantially V_(cc) -2.V_(BE) is delivered to the output terminalP₂.

In contrast, when the ECL signal A takes the high level, the states ofthe differential pair transistors Q₁₃, Q₁₄ are reversed to that of thecase in which the same signal takes the low level. Namely, by a suitableselection of the resistance value of the resistor R₂₀, the node N₂ takesa low level substantially equal to the grounding potential GND. In thisstate, the darlington connection transistors Q₁₈, Q₁₉ are turned on bythe high level potential at the node N₁, and the darlington connectiontransistors Q₁₆, Q₁₇ are turned off by the low level potential at thenode N₂. In consequence, a low level signal substantially equal to thegrounding potential GND is delivered to the output terminal P₂.

In the circuit shown in FIG. 1, as the absolute value of the negativesource voltage -V_(EE) is lowered, the bias voltage supplied to thetransistor Q₁₀ becomes insufficient so that the emitter output currentfrom this transistor Q₁₀ is reduced. Accordingly, the collector currentof the current source transistor Q₁₅ of the level conversion section 1is reduced.

Assuming here that the source voltage detecting section 5, negativevoltage detecting section 4-1 and the positive voltage detecting section4-2 are omitted from the circuit shown in FIG. 1, the output signal fromthe level conversion circuit is undesirably changed by theabove-mentioned voltage fluctuation and, in addition, the single endpush-pull transistors Q₁₆ to Q₁₉ are undesirably turned on to permitelectric currents to flow therethrough.

More specifically, if one of the differential pair transistors, e.g. thetransistor Q₁₃, of the level conversion section 1 takes the on state inresponse to the low level signal applied to the input A, the voltagedrop across the resistor R₁₉ is decreased in accordance with thereduction of the collector current of the above-mentioned current sourcetransistor Q₁₅. In consequence, the low level signal potential at thenode N₁ is increased and, consequently, the transistors Q₁₈ and Q₁₉ areturned on undesirably. In this state, the level of the signal at theoutput terminal P₂, which is bound to take a high level by thetransistors Q₁₆, Q₁₇ receiving the high level signal from the node N₂,starts to decrease undesirably toward the low level.

To the contrary, when the other differential transistor Q₁₄ takes the onstate in response to the high level signal applied to the input A, thevoltage drop across the resistor R₂₀ is decreased in accordance with thedecrease of the collector current of the current source transistor Q₁₅,so that the potential of the low level signal at the node N₂ is raisedto undesirably turn the transistors Q₁₆, Q₁₇ on. In this state, thelevel of the signal at the output terminal P₂, which is bound to takethe low level by the transistors Q₁₈, Q₁₉ receiving the high levelsignal from the node N₁, is undesirably increased toward the high level,by the starting of turning on of the transistors Q₁₆, Q₁₇.

As the positive source voltage V_(cc) is increased out of thepredetermined range, the low level signal at the node N₁ or N₂ isundesirably increased toward the high level, because the voltage dropacross the resistor R₁₉ or R₂₀ of the level conversion circuit 1 takes asubstantially constant value which is determined by the current in thecurrent source transistor Q₁₅. For instance, when the level of thesignal applied to the input A is low, the potential at the node N₁,which should take the low level, is increased toward the high level inaccordance with the increase of the positive source voltage V_(cc).Therefore, the transistors Q₁₈, Q₁₉ which should take the off state areundesirably turned on in accordance with the increase of the potentialat the node N₁.

To the contrary, when the positive source voltage V_(cc) has come downbelow the predetermined range, the high level of the signal delivered tothe output terminal P₂ can no more be regarded as being distinctive highlevel for the circuit connected to the output terminal P₂, e.g. the TTLcircuit or N-MOS circuit.

As the signal at the terminal P₂ takes the undesirable level, the TTLcircuit or the N-MOS circuit receiving the signal from the terminal P₂does not operate at all or mal-functions.

The time lengths till the correct positive and negative source voltagesV_(cc), -V_(EE) are established after turning on of the power supplydiffer depending on the circuit arrangements. If the turning on of thenegative source -V_(EE) materially lags behind the turning on thepositive power source V_(cc), the nodes N₁ and N₂ take the high level,substantially simultaneously within the time lag.

If the nodes N₁ and N₂ take the high level simultaneously due to aninsufficient negative source voltage -V_(EE), an excess of the positivepower source V_(cc) or time difference between the turning on ofpositive source and that of the negative source, the signal level at theoutput terminal P₂ is undesirably changed as stated above. At the sametime, the push-pull output transistors Q₁₇ and Q₁₉ which are connectedbetween the positive power supply terminal P₁ and the grounding terminalP₃ are simultaneously turned on, so that through current flows intothese transistors Q₁₇, Q₁₉ from the power supply V_(cc), causing adanger of deterioration or, in the worst case, breakdown of thesetransistors.

To avoid this, it is possible to insert a current limiting resistor (notshown) in the series circuit of the output transistors Q₁₇ and Q₁₉, toreduce the through current. This, however, poses a problem that, sincethe output current at the output terminal P₂ is undesirably limited bythe above-mentioned current limiting resistor, it becomes difficult tosupply the output terminal P₂ with a signal which drives the capacitiveload at a high speed.

According to the invention, the undesirable change of the output signallevel from the output terminal P₂, as well as the undesirable generationof the through current, is fairly avoided without requiring the use ofthe current limiting resistance, thanks to the use of the source voltagedetecting section 5 and materially integral negative voltage detectingsection 4-1 and positive voltage detecting section 4-2.

The source voltage detecting section 5 is constituted by resistors R₁₁to R₁₃ and transistors Q₅ to Q₈ as illustrated. In the illustratedcircuit, the transistors Q₆ and Q₈ are turned on when the biasingvoltage at the node N₃ of the biasing section 2 becomes greater than thesum 2 V_(BE) of the base-emitter forward voltage V_(BE), and turned offwhen the same is decreased below 2 V_(BE).

As stated before, the biasing voltage at the node N₃ takes a valuesmaller than 2 V_(BE) when the positive and negative source voltagesV_(cc), -V_(EE) are within correct ranges. In this state, thetransistors Q₈ is kept off, and, therefore, does not limit at all thesignal appearing at the node N₂ of the level conversion section 1.

The biasing voltage at the node N₃ becomes greater than 2 V_(BE) as thepositive source voltage V_(cc) becomes excessively large or as thenegative source voltage -V_(EE) becomes excessively small. Accordingly,the transistor Q₈ is turned on to cause the transistor Q₂₀ to be turnedon. Consequently, the node N₂ of the level conversion section 1 isgrounded by the transistors Q₈, Q₂₀ to take the low level substantiallyequal to the grounding potential GND. In consequent, the undesirablesimultaneous turning on of transistor Q₁₇ and Q₁₉ controlled by thenodes N₁ and N₂ is fairly avoided.

FIG. 2 shows respective operating regions of the voltage detectingsections 4-1, 4-2 and 5, representing the positive source voltage V_(cc)and the negative source voltage |V_(EE) | by axis of ordinate and axisof abscissa, respectively. In this Figure, a symbol D represents aregion within the normal ranges of the positive and negative sourcevoltages V_(cc) and -V_(EE).

The transistor Q₈ of the source voltage detecting section 5 in FIG. 1 isturned on at the region A above the line l₁ in FIG. 2.

The negative source voltage detecting section 4-1 includes, asillustrated, resistors R₃, R₄ connected in series between the groundingterminal P₃ and the negative power supply terminal P₇, diodes D₅ to D₈and a transistor Q₂ connected at its base to the common connection pointof the diode D₈ and the resistor R₄.

The above-mentioned transistor Q₂ is turned on and off as the absolutevalue |V_(EE) | of the negative source voltage becomes higher and lowerthan the sum 5 V_(BE) of the forward voltages V_(BE) of the diodes D₅ toD₈ and the base-emitter forward voltage V_(BE) of the transistor Q₂.

The positive source voltage detecting section 4-2 includes resistors R₁,R₂ and diodes D₁ to D₄ connected in series between the positive powersupply terminal P₁ and the grounding terminal P₃, and a transistor Q₁connected at its base to the common connection point between the diodeD₄ and the resistor R₂. The collector of the transistor Q₁ is connectedto the positive power supply terminal P₁ through the resistor R₅. Thetransistor Q₃ has a base connected to a common connecting point betweenthe collector of the above-mentioned transistor Q₁ and the resistor R₅,while the collector and emitter thereof are connected commonly to thetransistor Q₈.

The emitter of the transistor Q₁ is connected to the collector of thetransistor Q₂ of the aforementioned negative source voltage detectingsection 4-1 through a diode D₉. The cathode of the diode D₉ is connectedto the grounding terminal P₃ through the diode D₁₀.

The potential at the emitter of the transistor Q₁ is maintainedsubstantially at the grounding level GND when the transistor Q₂ of thenegative source voltage detecting section 4-1 takes the on state due tothe actions of the diodes D₉ and D₁₀, and is floating when thetransistor Q₂ takes the off state.

The transistor Q₁ takes the on state when the positive source voltageV_(cc) is greater than about 5 V_(BE) while the above-mentionedtransistor Q₂ is in the on state, and takes the off state when thepositive source voltage V_(cc) is below 5 V_(BE) or when the transistorQ₂ takes the off state.

The negative source voltage detecting circuit 4-1 and the positivesource voltage detecting circuit 4-2 are substantially integral witheach other. When at least one of the positive and negative sourcevoltages, V_(cc) and -V_(EE), in absolute value becomes below apredetermined level, caused from taking the off state of at least one ofthe transistor Q₁ and Q₂, the transistor Q₁ is turned off. Therefore, inthis case, the collector of the transistor Q₁ having the load resistanceR₅ provides a high level signal.

When the absolute values of the positive source voltage V_(cc) and thenegative source voltage -V_(EE) takes the values exceeding predeterminedlevels simultaneously, the transistor Q₁ takes the on state, so that alow level signal of a level substantially equal to the groundingpotential GND is obtained at the collector of the transistor Q₁.

The transistor Q₃ is turned on by the high level signal derived from thecollector of the transistor Q₁ and is turned off by the low level signalfrom the same.

As will be understood from the foregoing description, if the absolutevalue of the positive source voltage V_(cc) or the negative sourcevoltage -V_(EE) is smaller than a predetermined level, the transistor Q₃takes the off state so that the emitter of the transistor Q₂₀ takes alevel substantially equal to the grounding potential GND. Therefore, ashas been described already, the node N₂ of the level conversion section1 takes a low level substantially equal to the grounding potential GND,so that the nodes N₁ and N₂ are prevented from simultaneously taking thehigh level.

The negative source voltage detecting section 4-1 makes the node N₂ takethe low level when the negative source voltage -V_(EE) is at the regionB to the left from a line l₂ of FIG. 2, while the positive sourcevoltage detecting section 4-2 functions to make the node N₂ take the lowlevel when the positive source voltage V_(cc) is in the region C below aline l₃ in FIG. 2.

In the level conversion circuit shown in FIG. 1, the output terminal P₂produces an output the level of which is forcibly maintained at the lowlevel within these regions A and B. It is, therefore, possible toeliminate the through current flowing in the transistors Q₁₇ and Q₁₉. Itis, therefore, possible to protect the output transistors Q₁₇ and Q₁₉from deterioration or breakdown caused by the through current.

The emitter of the transistor Q₁₂ of the level conversion section 1 isconnected to the emitters of the differential pair transistors Q₁₃, Q₁₄while the collector thereof is connected to the collectors of thetransistors Q₃ and Q₈. The transistor Q₁₂ receives at its base a biasingvoltage of a level lower than the low level of the ECL signal whichtakes, for example, a high and low levels of -0.89 V and -1.69 V,respectively. Therefore, this transistor Q₁₂ takes the off state whenthe terminal P₄ receives an ECL signal A or when the terminal P₅ is inreceipt of the bias voltage V_(B) or the ECL signal B.

The transistor Q₁₂ takes the on state, when the input terminals P₄ andP₅ open simultaneously to simultaneously turn off the differentialtransistors Q₁₃ and Q₁₄. In consequence, the emitter of the transistorQ₂₀ takes the low level substantially equal to the grounding potential,so that the node N₂ is forcibly maintained at the low level as has beendescribed already. The protective transistor Q₃ controlled by thepositive and negative source voltage detecting sections 4-1, 4-2, theprotective transistor Q₈ which is controlled by the source voltagedetecting section 5 and the protective transistor Q₁₂ of the levelconvension section 1 in combination prohibit the nodes N₁ and N₂ fromsimultaneously taking the high level due to various reasons.

If the transistor Q₂₀ is eliminated and the collector of the protectivetransistors Q₃, Q₈ and Q₁₂ are commonly connected to the node N₂, thecollector capacitances of these protective transistors Q₃, Q₈ and Q₁₂are added to the collector capacitance of the differential transistorQ₁₄. This direct connection of collector capacitances of a multiplicityof transistors to the node N₂ seriously lowers the switching speed ofthe node N₂.

In the circuit shown in FIG. 1, the protective transistors Q₃, Q₈ andQ₁₂ are connected, in accordance with the technical idea of theinvention, at their collectors to the emitter of the transistor Q₂₀specifically provided for the separation of capacitance, so that thecollector capacitances of these protective transistors Q₃, Q₈ and Q₁₂can be separated from the node N₂. In consequence, only the collectorcapacitance of the transistor Q₂₀ is added to the capacitance of thenode N₂, to realize a high-speed switching operation of the node N₂.

The described embodiments are not exclusive and can be modified invarious manners. For instance, the output formed by a resistor R₂₅between the common collectors of the protective transistors Q₃, Q₈ andQ₁₂ and the power supply terminal P₁ may be delivered to an invertercircuit constituted by a transistor and a resistor, the output from theinverter circuit being used for driving an npn transistor newlyconnected between the grounding terminal P₃ and the node N₂ or N₁.Alternatively the above-mentioned newly connected transistor may bedriven by the output of a NAND circuit which receives outputs fromcollector load circuits of the protective transistors. It is alsopossible to use a diode, particularly a Schottky diode which can providespecifically small junction capacity, in place of the capacitanceseparation transistor Q₂₀ of the described embodiment. Further, it ispossible to construct the capacitance separating transistor as amulti-emitter transistor having a multiplicity of emitters which receiveoutputs from load resistors connected to the collectors of theprotective transistors.

The described forms of the source voltage detecting circuits 4-1, 4-2and 5, as well as biasing circuits 2, 3, are not exclusive and may bemodified and changed in various ways.

FIG. 3 is a circuit diagram of another embodiment of the invention. Thelevel conversion circuit of this embodiment is used in the interfacebetween the output of a emitter-coupled logic (referred to as ECL,hereinunder) circuit and the input of a circuit such as atransistor-transistor logic (referred to as TTL) circuit or an N-channelinsulated gate type field effect transistor (referred to as N-MOS)circuit.

Although not exclusive, the illustrated circuit is formed as amonolithic integrated circuit (IC) by the known technique, to haveexternal terminals P₁ to P₇.

The above-mentioned terminal P₁ is adapted to receive a source voltageof +5 V, while the terminal P₇ receives a negative voltage of -5.2 V.The terminal P₃ is connected to the grounding potential GND.

The portion enclosed by two-dot-and-dash line 1 is a differentialswitching circuit constituted by a current source transistor Q₁₅ havingan emitter resistor R₂₄, differential pair transistors Q₁₃, Q₁₄ andcollector resistors R₁₉, R₂₀ of respective differential pairtransistors.

A level substantially midpoint of the ECL signal level, e.g. a voltageof -1.29 V, is applied to the base of the above-mentioned differentialpair transistor Q₁₃ through terminals P₆, P₅ from the biasing circuit 2.Therefore, the differential pair transistors Q₁₃ or Q₁₄ are turned on byapplication of ECL signal A to the base of the transistor Q₁₄ via theterminal P₄, so that a constant current from the current sourcetransistor Q₁₅ is made to flow through the resistor R₁₉ or R₂₀ togenerate a voltage drop. In consequence, signals of reverse phases arederived from the collectors of the transistors Q₁₃, Q₁₄ in accordancewith the input signal of ECL level. In this case, resistors R₁₉ and R₂₀are set at suitable levels so that the low levels of the collectoroutput signals of these transistors Q₁₃, Q₁₄ takes a value substantiallyequal to the grounding potential, e.g. +0.3 V.

The collector outputs from the transistors Q₁₃, Q₁₄ are connected to thebases of the transistors Q₁₇, Q₁₉ of cascade connection, through emitterfollower transistors Q₁₆, Q₁₈. In consequence, the output transistorsQ₁₇ and Q₁₉ are actuated in reverse phases by the collector outputs fromthe differential pair transistors Q₁₃, Q₁₄.

In consequence, the output terminal P₂ produces an output signal OUTwhich is converted into positive voltage system corresponding to thenegative voltage system input A of ECL level and which is strong enoughto drive a heavy load such as capacitive load, e.g. an N-MOS memory.

This embodiment employs a protective circuit 6 adapted to forciblymaintain at the low level one of the output points of the differentialswitching circuit, e.g. N₁, when the source voltages V_(cc) and -V_(EE)are out of predetermined ranges.

The output point N₈ of the protective circuit 6 is connected to theoutput point N₁ of the differential switching circuit 1 through thecapacitance dividing circuit 10 of the invention.

The protective circuit 6 includes a circuit 4' for detecting thepositive and negative source voltages V_(cc), -V_(EE), a circuit 5' fordetecting the negative source voltage -V_(EE), a biasing circuit 2' andprotective transistors Q₃, Q₈ and Q₁₂. These detecting circuits 4', 5'are adapted to keep the protective transistor Q₃ or Q₈ in the on statewhen the source voltage falls out of the predetermined ranges. As aresult, the output point N₁ can be maintained at a low level.

The protective transistor Q₁₂ is provided for preventing the outputs ofthe differential pair transistors Q₁₃, Q₁₄ from simultaneously taking ahigh level when the inputs of these transistors are openedsimultaneously.

In the embodiment shown in FIG. 3, the output point N₈ of the protectivecircuit 6 and one output point N₁ of the differential switching circuit1 are connected to each other through a diode D₁ whose cathode isconnected to the above-mentioned output point N₈. Further, the outputpoint N₈ and the power supply terminal P₁ are connected to each otherthrough the resistor R₂₉.

As will be explained hereinunder, the capacitance dividing circuit 10 ofthe invention including the resistor R₂₉ and the diode D₁₉ has afunction for enhancing the speed of rise of the potential at the outputpoint N₁ from the low level to the high level.

FIGS. 4 and 5 are illustrations of these functions. More specifically,FIG. 4 shows an equivalent circuit of a portion of the circuit shown inFIG. 3 including the resistors R₁₉, R₂₉, diode D₁₉ and the transistorQ₁₃. Capacitances C₁, C₂ are parasitic capacitances connected to theoutput points N₁ and N₈.

The capacitance C₂ is the capacitances of the protective transistors Q₃,Q₈ and Q₁₂, while the capacitance C₁ is the capacitances possessed bytransistors Q₁₃, Q₁₈ and so forth.

Representing here the potentials at the output points N₁, N₈ by V₁ andV₂, respectively, wave forms of voltages V₁, V₂ are obtained as shown inFIG. 5. The wave form shown by broken line is obtained when theresistance R₂₉ is not connected.

The following explanation is made on an assumption that the protectivetransistors Q₃, Q₈ and Q₁₂ always take off state.

The voltages V₁, V₂ are maintained substantially at the same level asV_(cc) when the transistor Q₁₃ is in the off state, because thecapacitances C₁, C₂ are charged through the resistors R₁₉, R₂₉.

Then, as the transistor Q₈ is turned on at an instant t₁, the electriccharge of the capacitance C₁ is discharged through the transistor Q₁₃ sothat the voltage V₁ is made to approach the grounding potential GND. Atthis time, the diode D₁₉ is biased in backward direction. Meanwhile, theelectric charge of the capacitance C₂ is discharged by a leakage currentwhich flows through the resistance R₀. Therefore, in order to hold thevoltage V₂ substantially at the level of V_(cc), the resistance value ofthe resistor R₂₉ should be selected to be sufficiently small as comparedwith the resistance value of the leakage resistance R₀. In consequence,the resistance value of the resistor R₂₉ is selected to fall betweenabout 1 KΩ to 100 KΩ.

On the other hand, in the event that the resistance R₂₉ is notconnected, the electric charge of the capacitance C₂ is graduallydischarged by the leakage current flowing through the resistor R₀, sothat the voltage V₂ gradually approaches GND. This process is shown bybroken line in FIG. 5.

Then, as the transistor Q₁₃ is turned off at an instant t₂, thecapacitance C₁ is charged up through the resistor R₁₉. In consequence,the voltage V₁ rises with a time constant C₁ R₁₉ and reachessubstantially V_(cc) at the instant t₄.

On the other hand, when the resistor R₂₉ is not connected, the voltageV₂ gradually approaches GND as explained before. Therefore, representingthe forward voltage of the diode D₁₉ by V_(FD1), the diode D₁₉ is biasedin forward direction at an instant t₃ at which the voltage V₁ becomesgreater than the sum of the voltage V₂ +V_(FD1). In consequence, thecapacitance C₂ is charged through the resistor R₁₉ and the diode D₁₉. Inconsequence, a time constant (C₁ +C₂) R₁₉ is formed to delay the instantt₅ at which the voltage V₁ reaches a level substantially equal toV_(cc). This state is shown by broken line of FIG. 5.

As has been described, the resistor R₂₉ and the diode D₁₉ function tomaintain the voltage V₂ of the output point N₈ substantially at the samelevel as V_(cc) to maintain a constant electric charge charging thecapacitance C₂, so that the capacitance C₂ as viewed from the outputpoint N₁ can be neglected equivalently. It is, therefore, possible toenhance the speed of rise of the voltage V₁ at the output point N₁. Inthis embodiment, it is preferred to use a Schottky barrier diode whichcan provide a specifically small junction capacitance, as the diode D₁₉.

FIG. 6 shows a modification in which a transistor Q₂₅ is used as theswitching element between the output points N₁ and N₈ of the embodimentshown in FIG. 4. The transistor Q₂₅ has the collector and emitterconnected to the output points N₁ and N₈, respectively, while the basethereof is connected to the source voltage V_(cc) through the resistorR₂₈.

In this modification also, the resistor R₂₉ and the transistor Q₂₅function to maintain the potential V₂ at the output point N₈ of theprotective circuit 6 substantially at the same level as V_(cc) to keep aconstant electric charge charging the capacitance C₂, so that thecapacitance C₂ as viewed from the output point N₁ of the switchingcircuit 1 can be equivalently neglected. It is, therefore, possible toenhance the speed of rise of the voltage V₁ at the output point N₁.

The above-described embodiment is not exclusive. For instance, theswitching circuit 1 and the protective circuit 6 for the latter may beconstituted by insulated gate type field effect transistors.

What is claimed is:
 1. A level conversion circuit comprising:a first anda second input transistor connected to each other at their emitters in adifferential manner, the base of said first input transistor beingconnected to receive a predetermined voltage level; a first loadconnected between the collector of said first input transistor and apositive source voltage; a second load connected between the collectorof said second input transistor and said positive voltage; a currentsource connected between the emitters of said first and second inputtransistors and a negative source voltage; a first output transistorhaving a base adapted to be driven by the output from the collector ofsaid second input transistor, a collector connected to said positivesource voltage and an emitter connected to an output terminal; a secondoutput transistor having a base adapted to be driven by the collectoroutput of said first input transistor, a collector connected to saidoutput terminal and an emitter connected to a grounding terminal; asource voltage detecting circuit adapted to detect at least one of saidpositive and negative source voltages and to provide an output signalindicating a state of the level thereof; a first protective transistorhaving a base to which is applied a biasing voltage of a level lowerthan the predetermined voltage level to be applied to said first inputtransistor, a collector connected to said positive source voltagethrough a third load and an emitter connected to said emitters of saidfirst and second input transistors; a second protective transistorhaving a base adapted to receive the output signal from said sourcevoltage detecting circuit, an emitter connected to the groundingterminal and a collector connected to the collector of said firstprotective transistor; and a capacitance separation element disposedbetween said collector of said second input transistor and saidcollectors of said first and second protective transistors.
 2. A levelconversion circuit as claimed in claim 1, wherein said source voltagedetecting circuit includes means to turn on said second protectivetransistor when said positive source voltage is excessively high or whensaid negative source voltage is excessively low.
 3. A level conversioncircuit as claimed in claim 2, wherein said capacitance separationelement is a capacitance separating transistor having an emitterconnected to said collectors of said first and second protectivetransistors, a base connected to said positive source voltage through aresistor and a collector connected to said collector of said secondinput transistor.
 4. A level conversion circuit as claimed in claim 2,wherein said capacitance separation element is a capacitance separationdiode having a cathode connected to the collector of said first andsecond protective transistors and an anode connected to the collector ofsaid second input transistor.
 5. A level conversion circuit as claimedin claim 3 or 4, wherein an output of said level conversion circuit isderived from said output terminal and is delivered to an input terminalof an N-MOS circuit.